This invention relates to a semiconductor device-mounting construction having solder bumps serving as external terminals, and more particularly to a semiconductor device-mounting construction capable of achieving an excellent connection reliability of solder bumps. This invention also relates to a method of inspecting such a semiconductor device-mounting construction.
With the highly-integrated design of semiconductor devices, there have now been developed semiconductor devices having an increased number of external terminals (pins). There have been used two methods of achieving such a semiconductor, and one is a method in which in a conventional quad flat package (hereinafter referred to as xe2x80x9cQFPxe2x80x9d) having leads serving as external terminals, the pitch of the terminals is made finer and smaller, thereby increasing the number of pins. According to this method, there has been developed a QFP of the type in which the terminal pitch is reduced to 0.3 mm. However, the terminals are arranged in a one-dimensional manner, and therefore it is said that the upper limit is 400 pins in view of the dimensions of the semiconductor device which can be mounted.
The other method is one in which solder bumps are arranged in a two-dimensional manner on a reverse surface of a semiconductor device, and are used as external terminals. A semiconductor device of this construction is commonly called a ball grid array (hereinafter referred to as xe2x80x9cBGAxe2x80x9d). The detailed construction of a BGA is disclosed, for example, U.S. Pat. No. 5,216,278 and NIKKEI ELECTRONICS No. 601, page 59.
Recently, there have been developed a BGA-type semiconductor device whose size is reduced to the size of a semiconductor chip. This is called a chip-size package (hereinafter referred to as xe2x80x9cCSPxe2x80x9d). The detailed construction of a CSP is disclosed in NIKKEI ELECTRONICS No. 668, page 139. Further, Japanese Patent Laid-Open Publication No. 6-504408 (W092/05582) discloses a CSP of the type in which a tape, having external terminals, is provided on a circuit-forming surface of a semiconductor chip through a soft or elastic material (elastomer resin), and the external terminals are electrically connected to electrodes of the semiconductor chip. Japanese Patent Unexamined Publication No. 6-224259 discloses a construction in which a semiconductor chip is mounted on a ceramic substrate having through holes, and electrodes are formed on the opposite surface of the ceramic substrate, and the semiconductor device is mounted on a printed circuit board. Japanese Patent Unexamined Publication No. 6-302604 discloses a CSP of the type in which a metallic wiring pattern is formed on a circuit-forming surface of a semiconductor chip, and external terminals are provided on this wiring pattern.
What becomes a large problem with the BGA-type semiconductor device, using the solder bumps as the external terminals, is the connection reliability of the solder bumps. If the coefficient of linear expansion of the semiconductor device is different from that of a mounting board, a strain develops in the solder joint portions in accordance with a temperature change, and when this is repeated, a thermal fatigue failure may occur. In the conventional semiconductor device, such as a QFP, having leads serving as external terminals, the leads absorb this thermal deformation, thereby reducing a strain developing in the solder, so that the thermal fatigue failure can be prevented. However, in the BGA-type semiconductor device, thermal deformation is applied directly to the solder bumps.
Therefore, in the type of BGA-type semiconductor device (as disclosed in U.S. Pat. No. 5,216,278) using a printed circuit board, there is employed a method in which the printed circuit board of the semiconductor device and a mounting printed circuit board are made equal in the coefficient of linear expansion to each other, thereby preventing thermal deformation. However, even if the two printed circuit boards are made of the same kind of material, the two boards are different in the coefficient of linear expansion from each other usually by an amount of about 2xc3x9710xe2x88x926/xc2x0 C. because of variations in the coefficient of linear expansion of the material.
Among the above-mentioned prior art devices, it is thought that the semiconductor device, disclosed in Japanese Patent Laid-Open Publication No. 6-504408, is the type in which the solder fatigue failure is most taken into consideration, and the reliability is the highest. In this semiconductor device, the tape, having the external terminals, is provided on the semiconductor chip through the elastomer resin, and the external terminals are electrically connected to the electrodes of the semiconductor chip, and the solder bumps are joined to the external terminals. Therefore, the thermal deformation due to the difference in the coefficient of linear expansion between the semiconductor chip and the mounting board can be absorbed by the elastomer, thereby preventing the thermal fatigue failure of the solder bumps. However, the size of this semiconductor device coincides with the size of the semiconductor chip, and therefore the number of pins is limited.
And besides, voids, which are due to insufficient wetting and the involvement of gas during joining of the solder, are present in the solder joint portion. From the study by the inventors of the present invention, it is clear that these voids are a factor reducing a fatigue life of the solder joint portion, and its contents are described in xe2x80x9cCurrent Japanese Material Research, No. 2(1987), pp.235xe2x80x9d published by the Society of Materials Science, Japan. With respect to this problem, the target of the process design is to reduce the ratio of the total area of voids to the total cross-sectional area of the joint portion (commonly referred to as xe2x80x9cvoid ratioxe2x80x9d). Namely, efforts have been made to reduce the total area of the voids.
As described above, the conventional BGA-type semiconductor devices still have the problem with respect to the connection reliability of the solder bumps regardless of their construction. Particularly, no consideration has been given to a reduced thermal fatigue life due to the influence of the voids existing in the solder bump joint portion.
It is an object of this invention to provide a BGA-type semiconductor device which overcomes the drawbacks of the above conventional BGA-type semiconductor devices, and achieves an excellent connection reliability of solder bumps.
The above object has been achieved by limiting voids, present in a solder joint portion of a BGA-type semiconductor device, to a predetermined size.
A semiconductor device-mounting construction of the present invention comprises a semiconductor device having a plurality of electrodes formed on one main surface thereof, a printed circuit board having a wiring pattern formed on one main surface thereof, and a plurality of solder bumps interposed between the plurality of electrodes and the wiring pattern to electrically connect the semiconductor device and the printed circuit board together, and this semiconductor device-mounting construction has the following features:
(1) All of voids, which are present in an interface of each of those of the plurality of solder bumps (which are disposed closest to an outer peripheral edge of the semiconductor device), joined to the semiconductor device, are fine, and generally uniform in size.
A shearing strain, developing in the solder bump, becomes larger as the distance between the solder bump and the center of the semiconductor device becomes larger, and therefore those solder bumps, disposed closest to an outer periphery edge of the semiconductor device, are subjected to a severest condition. Therefore, if all of the voids, which are present in the interface of the solder bump under this severest condition, are fine, and generally uniform in size (that is, uniform voids), the concentration of the strain will not occur, so that the reliability of the solder bump joint portion is enhanced.
The term xe2x80x9cuniform voidsxe2x80x9d, which are fine and generally uniform in size, does not mean that these voids are exactly uniform or equal in size, but variations in void size are allowed. In an ordinary solder joint formed in the atmosphere, a variation of two times void size is allowable.
(2) The diameter of all of the voids, which are present in the interface of each of those of the plurality of solder bumps (which are disposed closest to the outer peripheral edge of the semiconductor device), joined to the semiconductor device, is not more than {fraction (1/10)} of the diameter of the interface.
If the diameter of the voids, present in the interface of the solder bump under the severest condition, is not more than {fraction (1/10)} of the diameter of the interface, the concentration of the strain in the voids will not occur, so that the reliability of the solder bump joint portion is enhanced.
The interface, as well as the voids, are generally circular in shape, but strictly, if equivalent diameters [the equivalent diameter of the interface={square root over ( )}(4xc3x97a cross-sectional area of the interface/xcfx80), the equivalent diameter of the void={square root over ( )}(4xc3x97a cross-sectional area of the void/xcfx80)] are used respectively as the diameter of the interface and the diameter of the void, the present invention can be applied.
(3) In the semiconductor device-mounting construction according to Paragraph (1) or Paragraph (2), a length of one side of the semiconductor device is not less than 30 mm.
In the semiconductor device whose one side is more than 30 mm, no margin is left for the fatigue strength of the ordinary reliability standard, and it is necessary that the semiconductor device-mounting construction of Paragraph (1) or Paragraph (2) should be used.
(4) In the semiconductor device-mounting construction according to any one of Paragraphs (1), (2) and (3), the number of the electrodes of the semiconductor device is not less than 441.
In the semiconductor device in which the number of electrodes is not less than 441, no margin is left for the fatigue strength of the ordinary reliability standard, and it is necessary that the semiconductor device-mounting construction of any of Paragraphs (1) to (3) should be used.
A method of the present invention for inspecting a connection reliability of solder bumps in a semiconductor device-mounting construction (comprising a semiconductor device having a plurality of electrodes formed on one main surface thereof, a printed circuit board having a wiring pattern formed on one main surface thereof, and a plurality of solder bumps interposed between the plurality of electrodes and the wiring pattern to electrically connect the semiconductor device and the printed circuit board together) has the following features:
(5) When a diameter of the largest one of voids, which are present in an interface of each of the solder bumps joined to the semiconductor device, exceeds a predetermined value, the semiconductor device-mounting construction is decided as a rejected one.
(6) In the method according to Paragraph (5), the predetermined value is not more than {fraction (1/10)} of the diameter of the interface.
A strain, developing in the solder, is determined by the size of a concentration void rather than by the ratio of the void area. Therefore, it is only necessary to inspect the largest void at the interface between the solder bump and the semiconductor device. Specifically, a sampling destructive test or a x-ray fluoroscopic test is effected, and when the value of the largest void exceeds a predetermined value, the semiconductor device-mounting construction is decided as a rejected one.